1. Field of the Invention
The present invention relates in general to a semiconductor device, and in particular to a semiconductor device utilizing a vertical surround gate MOSFET (will be referred to as a xe2x80x9cV"PHgr"Txe2x80x9d hereinafter). The invention also relates to a method of manufacturing such a semiconductor device. The invention further relates to an improvement of V"PHgr"T.
2. Description of the Background Art
FIG. 114 shows trend of cell sizes of dynamic random access memories (DRAMs). FIG. 114 additionally shows design rules in respective generations. Conventional DRAM cells include, as components, bit lines (BL), word lines (WL), bit line contacts (BK), and storage contacts (SK). Therefore, the cell size, which is expressed with F (feature size) of the following formula, is 8F2.
F (feature size)=r+xcex1
wherein F represents a gate width, r represents a minimum line width and xcex1 represents a process margin.
In FIG. 114, the design rule (minimum line width) is simply set to F, and 8F2 and 4F2 (hollow and solid circles) are plotted in a superimposed form. As can be seen therefrom, the cells of 8F2 can form 256M-DRAM at the most. Meanwhile, the cell size of 4F2 can achieve a DRAM of G-bit generation by following the conventional reduction rule.
The cells of 4F2 can be formed by arranging vertical transistors at crossings of the bit lines BL and word lines Wl. Based on the above background, various kinds of vertical transistors have been proposed.
FIG. 115 is a cross section of a first prior art, which is a vertical surround gate transistor disclosed in Japanese Patent Laying-Open No. 5-160408 (1993). Referring to FIG. 115, a gate 3 is formed around a column 5 of silicon forming a channel with a gate insulating film 4 therebetween. A source 6a and a drain 6b are connected to silicon column 5.
A significant problem arises in connection with formation of gate electrode 3 forming the word line if the above transistor is applied to a DRAM.
FIG. 116 is a cross section of a semiconductor device showing a process of manufacturing the surround gate transistor shown in FIG. 115. Gate insulating film 4 is formed to cover silicon column 5. Then, polysilicon (3) is deposited to cover silicon column 5 with gate insulating film 4 therebetween. Anisotropic etching is effected on polysilicon (3) to form gate electrode 3 on a side wall of silicon column 5. According to this method, a gate length 1 depends on an anisotropic etching rate of polysilicon (3). Therefore, a variation v of the gate length l is large. According to this method, therefore, it is very difficult to obtain stably the cells of 4F2.
FIGS. 117 and 118 are cross sections showing steps in a process of manufacturing a vertical surround gate transistor disclosed in Japanese Patent Laying-Open No. 4-282865 (1992).
Referring to FIG. 117, an SiO2 layer 2a, polysilicon, i.e., word line 3 and an SiO2 layer 2b are formed in this order on a bit line 26. There is also provided a contact hole 8 penetrating SiO2 layer 2b, polysilicon 3 and SiO2 layer 2a. Gate insulating film 4 is formed on the side wall of contact hole 8.
Referring to FIGS. 117 and 118, the side wall of contact hole 8 is covered with polysilicon 5. Polysilicon 5 is divided into a source 6a, a channel 7 and a drain 6b. The transistor thus constructed has the following problem. Referring to FIG. 117, variation v of etching quantity is liable to occur when forming gate insulating film 4, and in some cases, an upper corner 3c of the gate electrode is exposed, resulting in leak between corner 3c of the gate and drain 6b. 
The transistor also has the following problem in connection with its operation.
The conductivity types of the gate polysilicon and channel polysilicon are opposite to each other, and a difference in their work function is utilized for depleting the channel polysilicon, whereby the off state is achieved between the source and drain. For this purpose, a film thickness of the channel polysilicon must be smaller than the maximum width of the depletion layer which depends on concentration of impurity in the channel polysilicon.
Meanwhile, if the resistance of source/drain is high, a sufficient on-current cannot be obtained. Therefore, it is necessary to increase the content of impurity in the channel polysilicon for lowering the resistance. In an ordinary TFT, the content of impurity in the source/drain is 1020/cm3 at the most. However, if impurity were introduced at the large content of 1020/cm3, the maximum width of depletion layer would be approximately 40 xc3x85. Therefore, due to restriction that the film thickness of the channel polysilicon must be smaller than the above value, it would probably be impossible to achieve stable manufacturing of the transistors without sacrificing characteristics.
In order to overcome the above problems, the inventors and others have proposed a vertical "PHgr"-shaped transistor (V"PHgr"T) as shown in FIG. 119 (Japanese Patent Laying-Open No. 5-345126 (1993)).
FIG. 119 is a perspective view showing a major portion of a V"PHgr"T. FIG. 120 is a cross section of the V"PHgr"T.
Referring to these figures, a MOSFET includes a substrate 1. Source region 6a is formed at a main surface of substrate 1. First interlayer insulating film 2a is formed on substrate 1. Gate electrode 3, which has a top surface substantially parallel to the surface of substrate, is formed on first interlayer insulating film 2a. Second interlayer insulating film 2b covering gate electrode 3 is formed on first interlayer insulating film 2a. A surface of source region 6a is partially exposed through a contact hole 19 which penetrates first interlayer insulating film 2a, gate electrode 3 and second interlayer insulating film 2b. Gate insulating film 4 covers the side wall of contact hole 19. In contact hole 19, there is formed a first semiconductor layer 20 of a P-type, which is in contact with a surface 9 of source region 6a and extends from the surface of source region 6a to the same level as a lower surface of gate electrode 3. In contact hole 19, there is also formed a channel semiconductor layer 7, which is in contact with a surface of first semiconductor layer 20 and extends from the surface of first semiconductor layer 20 to the same level as an upper surface of gate electrode 3. A second semiconductor layer 5 of the P-type, which is in contact with the surface of channel semiconductor layer 7 and forms drain region 6b, is formed on channel semiconductor layer 7.
A third interlayer insulating film 2c covering drain region 6b is formed on the substrate. Third interlayer insulating film 2c is provided with a connection hole 11a exposing a portion of the surface of drain region 6b. An aluminum electrode 10a is connected to drain region 6b through connection hole 11a. 
Although the structure shown in FIGS. 119 and 120 can overcome the problems of the technique shown in FIGS. 115 and 117, the bit line capacitance cannot be reduced below a restricted extent.
Accordingly, it is an object of the invention to provide a semiconductor device which includes a bit line having a reduced capacitance, improved to enable high-speed operation and utilizes a V"PHgr"T.
Another object of the invention is to provide a DRAM of a G-bit generation.
Still another object of the invention is to provide a DRAM having a cell size of 4F2.
Yet another object of the invention is to provide a method of manufacturing such a DRAM.
Further another object of the invention is to improve the V"PHgr"T described above.
Also, an object of the invention to provide an AND circuit using a V"PHgr"T.
A further object of the invention to provide an OR circuit using a V"PHgr"T.
A further object of the invention to provide an inverter circuit using a V"PHgr"T.
A further object of the invention to provide a flip-flop using a V"PHgr"T.
A further object of the invention to provide a gain cell using a V"PHgr"T.
A further object of the invention to provide a matrix of a liquid crystal display using a V"PHgr"T.
A first aspect of the invention relates to a semiconductor device, in which a gate transistor is operable to store information in a capacitor formed of a storage node, which is arranged at a crossing between a bit line and a word line, a capacitor insulating film and a cell plate electrode. The semiconductor device includes a substrate on which a dielectric layer and a semiconductor layer are formed successively. A first impurity diffusion layer of a second conductivity type is disposed in the semiconductor layer. The first impurity diffusion layer contains impurity of the first conductivity type implanted thereinto, and forms one of source/drain regions and the bit line. A first interlayer insulating film covering the first impurity diffusion layer is disposed on the substrate. A gate electrode which also forms the word line and has upper and lower surfaces is disposed on the first interlayer insulating film. A second interlayer insulating film covering the gate electrode is disposed on the first interlayer insulating film. A contact hole penetrating the first interlayer insulating film, the gate electrode and the second interlayer insulating film is provided for exposing a portion of a surface of the first impurity diffusion layer. A side wall of the contact hole is covered with a gate insulating film. A first semiconductor layer of the first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first impurity diffusion layer and extends from the surface of the first impurity diffusion layer to the substantially same level as the lower surface of the gate electrode. A channel semiconductor layer is formed in the contact hole. The channel semiconductor layer is in contact with the surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the gate electrode. A second conductive layer of the first conductivity type is disposed on the channel semiconductor layer. The second conductive layer is in contact with a surface of the channel semiconductor layer, and forms the storage node and the other of the source/drain regions. A capacitor insulating film is disposed on the second conductive layer.
A second aspect of the invention relates to a semiconductor device in which contact is to be made at a deep position. The device of this aspect includes a substrate on which a dielectric layer and a semiconductor layer are formed successively. A first impurity diffusion layer of a first conductivity type is disposed in the semiconductor layer. The first impurity diffusion layer forms a bit line and one of source/drain regions. A first F interlayer insulating film covering the first impurity diffusion layer is disposed on the substrate. A gate electrode which also forms the word line and has upper and lower surfaces is disposed on the first interlayer insulating film. A second interlayer insulating film covering the gate electrode is disposed on the first interlayer insulating film. A contact hole penetrating the first interlayer insulating film, the gate electrode and the second interlayer insulating film is provided for exposing a portion of a surface of the first impurity diffusion layer. A side wall of the contact hole is covered with a gate insulating film. A first semiconductor layer of the first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first impurity diffusion layer and extends from the surface of the first impurity diffusion layer to the substantially same level as the lower surface of the gate electrode. A second semiconductor layer of the same first conductivity type as the first semiconductor layer is formed in the contact hole. The second semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the gate electrode. A third semiconductor layer of the first conductivity type is formed in the contact hole and is disposed on the second semiconductor layer. The third semiconductor layer is in contact with a surface of the second semiconductor layer. An interconnection is connected to the third semiconductor layer.
A third aspect of the invention relates to a semiconductor device, in which a gate transistor is operable to store information in a capacitor formed of a storage node, which is arranged at a crossing between a bit line and a word line, a capacitor insulating film and a cell plate electrode. The device of this aspect includes a bit line having upper and lower surfaces. A first vertical "PHgr"-shaped transistor is disposed on the upper surface of the bit line. A capacitor is connected to the first vertical "PHgr"-shaped transistor. A second vertical "PHgr"-shaped transistor is disposed on the lower surface of the bit line. A second capacitor is connected to the second vertical "PHgr"-shaped transistor.
A fourth aspect of the invention relates to a semiconductor device in which flow of a large number of carriers is controlled by a voltage applied to a gate. The semiconductor device of this aspect includes a substrate having a main surface. A first conductive layer of a first conductivity type forming one of source/drain regions is disposed at the main surface of the substrate. A first interlayer insulating film is disposed on the substrate. A gate electrode having upper and lower surfaces is disposed on the first interlayer insulating film. A second interlayer insulating film covering the gate electrode is disposed on the first interlayer insulating film. A contact hole penetrating the first interlayer insulating film, the gate electrode and the second interlayer insulating film is provided for exposing a portion of a surface of the first conductive layer. A side wall of the contact hole is covered with a first gate insulating film. The semiconductor device further includes a silicon thin film which is in contact with the first conductive layer and continuously extends to cover an inner wall of the contact hole with the-first gate insulating film therebetween. The silicon thin film has a concave portion, which located in the contact hole and has a bottom surface located at a level lower than the lower surface of the first gate electrode. The silicon thin film is formed of three portions which are a cylindrical channel portion surrounded by the first gate electrode as well as a source region and a drain region located at vertically opposite sides of the channel portion. The device further includes a silicon oxide film which is disposed in the concave portion of the silicon thin film and is located at a level lower than an upper end of the channel portion. The concave portion of the silicon thin film is filled with polysilicon which is in contact with the channel portion. In this semiconductor device, the polysilicon is used as a lead electrode for fixing the potential of the channel portion.
A fifth aspect of the invention relates to a semiconductor device in which flow of a large number of carriers is controlled by a voltage applied to a gate. The semiconductor device of this aspect includes a substrate having a main surface. A first conductive layer of a first conductivity type forming one of source/drain regions is disposed at the main surface of the substrate. A first interlayer insulating film is disposed on the substrate. A gate electrode is disposed on the first interlayer insulating film. A second interlayer insulating film covering the gate electrode is disposed on the first interlayer insulating film. A contact hole penetrating the first interlayer insulating film, the gate electrode and the second interlayer insulating film is provided for exposing a portion of a surface of the first conductive layer. A side wall of the contact hole is covered with a conductive member. A surface of the conductive member is covered with a gate insulating film. A first semiconductor layer of the first conductivity type is disposed in the contact hole and is in contact with the surface of the first conductive layer. A channel semiconductor layer is disposed in the contact hole and is in contact with a surface of the first semiconductor layer. A second semiconductor layer of the first conductivity type forming the other of the source/drain regions is disposed in the contact hole and is in contact with a surface of the channel semiconductor layer.
A sixth aspect of the invention relates to a semiconductor device including an OR circuit. The semiconductor device of this aspect includes a substrate having a main surface. A first conductive layer of a first conductivity type forming one of source/drain regions is disposed at the main surface of the substrate. A first interlayer insulating film is disposed on the substrate. A first gate electrode and a second gate electrode which adjoin to each other and each have an upper surface and a lower surface are disposed on the first interlayer insulating film. A second interlayer insulating film covering the first and second gate electrodes is disposed on the first interlayer insulating film. A contact hole, which spreads over the first and second gate electrodes, and penetrates the first interlayer insulating film, the first and second gate electrodes and the second interlayer insulating film, is provided for exposing a portion of a surface of the first conductive layer. A side wall of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first conductive layer and extends from the surface of the first conductive layer to the substantially same level as the lower surface of the gate electrode. A channel semiconductor layer is formed in the contact hole. The channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from a surface of the first semiconductor layer to the substantially same level as the upper surface of the gate electrode. A second semiconductor layer of the first conductivity type forming the other of the source/drain regions is disposed on the channel semiconductor layer and is in contact with the surface of the channel semiconductor layer.
A seventh aspect of the invention relates to a semiconductor device including an AND circuit. The semiconductor device of this aspect includes a substrate, a first conductive layer of a first conductivity type disposed on the substrate, and a first interlayer insulating film disposed on the substrate and covering the first conductive layer. A first gate electrode having an upper surface and a lower surface is disposed on the first interlayer insulating film. A second interlayer insulating film covering the first gate electrode is disposed on the first interlayer insulating film. A second gate electrode having an upper surface and a lower surface is disposed on the second interlayer insulating film. A third interlayer insulating film covering the second gate electrode is disposed on the second interlayer insulating film. A contact hole, which penetrates the first interlayer insulating film, the first gate electrode, the second interlayer insulating film, the second gate electrode and the third interlayer insulating film, is provided for exposing a portion of a surface of the first conductive layer. Side walls of the first and second gate electrodes exposed in the contact hole are covered with a gate insulating film. A first semiconductor layer of a first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with a surface of the first conductive layer and extends from the surface of the first conductive layer to the substantially same level as the lower surface of the first gate electrode. A first channel semiconductor layer is formed in the contact hole. The first channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the first gate electrode. A Ad second channel semiconductor layer of a second conductivity type is formed in the contact hole. The second channel semiconductor layer extends from the lower surface of the second gate electrode to the substantially same level as the upper surface of the second gate electrode. A second semiconductor layer of the first conductivity type forming the other of the source/drain regions is disposed on the second channel semiconductor layer and is in contact with a surface of the second channel semiconductor layer.
An eighth aspect of the invention relates to a semiconductor device including an inverter circuit. The semiconductor device of this aspect includes a first n+-conductive layer. A first interlayer insulating film is disposed on the n+-conductive layer. A first gate electrode having an upper surface and a lower surface is disposed on the first interlayer insulating film. A second interlayer insulating film covering the first gate electrode is disposed on the first interlayer insulating film. A first contact hole, which penetrates the first interlayer insulating film, the first gate electrode and the second interlayer insulating film, is provided for exposing a portion of a surface of the first n+-conductive layer. A side wall of the first contact hole is covered with a first gate insulating film. A first n+-semiconductor layer is formed in the first contact hole. The first n+-semiconductor layer is in contact with a surface of the first n+-conductive layer and extends from the surface of the first n+-conductive layer to the substantially same level as the lower surface of the first gate electrode. A pxe2x88x92-semiconductor layer is formed in the first contact hole. The pxe2x88x92-semiconductor layer is in contact with a surface of the first n+-semiconductor layer and extends from the surface of the first n+-semiconductor layer to the substantially same level as the upper surface of the first gate electrode. A second n+-semiconductor layer is formed in the first contact hole and is disposed on the pxe2x88x92-semiconductor layer. The second n+-semiconductor layer is in contact with a surface of the pxe2x88x92-semiconductor layer and forms the other of the source/drain regions. A second n+-conductive layer is disposed on the second interlayer insulating film and is in contact with the second n+-conductive layer. A first p+-conductive layer is disposed on the second n+-conductive layer. A third interlayer insulating film is disposed on the first p+-conductive layer. A second gate electrode is disposed on the third interlayer insulating film. A fourth interlayer insulating film covering the second gate electrode is disposed on the third interlayer insulating film. A second contact hole penetrating the fourth interlayer insulating film, the second gate electrode and the third interlayer insulating film is provided for exposing a portion of a surface of the first p+-conductive layer. A side wall of the second contact hole is covered with a second gate insulating film. A first p+-semiconductor layer is formed in the second contact hole. The first p+-semiconductor layer is in contact with a surface of the first p+-conductive layer and extends from the surface of the first p+-conductive layer to the substantially same level as the lower surface of the second gate electrode. An nxe2x88x92-semiconductor layer is formed in the contact hole. The nxe2x88x92-semiconductor layer is in contact with the surface of the first p+-semiconductor layer and extends from the surface of the first p+-semiconductor layer to the substantially same level as the upper surface of the second gate electrode. A second p+-semiconductor layer forming the other of the source/drain regions is disposed in the contact hole. The second p+-semiconductor layer is disposed on the nxe2x88x92-semiconductor layer and is in contact with the surface of the nxe2x88x92-semiconductor layer. A second p+-conductive layer is disposed on the fourth interlayer insulating film and is in contact with the second p+-semiconductor layer.
A ninth aspect of the invention relates to a semiconductor device including a flip-flop circuit. The semiconductor device of this aspect includes a substrate and a first conductive layer of a first conductivity type disposed on the substrate. A first interlayer insulating film covering the first conductive layer is disposed on the substrate. A first gate electrode of the first conductivity type having an upper surface and a lower surface is disposed on the first interlayer insulating film. A second interlayer insulating film covering the first gate electrode is disposed on the first interlayer insulating film. A first contact hole, which penetrates the first interlayer insulating film, the first gate electrode and the second interlayer insulating film, is provided for exposing a portion of a surface of the first conductive layer. A side wall of the first contact hole is covered with a first gate insulating film. A first semiconductor layer of a first conductivity type is formed in the first contact hole. The first semiconductor layer is in contact with the surface of the first conductive layer and extends from the surface of the first conductive layer to the substantially same level as the lower surface of the first gate electrode. A first channel semiconductor layer of a second conductivity type is formed in the first contact hole. The first channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the first gate electrode. A second semiconductor layer of the first conductivity type forming the other of the source/drain regions is formed in the first contact hole. The second semiconductor layer is disposed on the first channel semiconductor layer and is in contact with the surface of the first channel semiconductor layer. A second gate electrode of the first conductivity type is disposed on the second interlayer insulating film and is in contact with the second semiconductor layer. A third interlayer insulating film covering the second gate electrode is disposed on the second interlayer insulating film. A second contact hole, which penetrates the third interlayer insulating film, the second gate electrode and the second interlayer insulating film, is provided for exposing a portion of a surface of the first gate electrode. A side wall of the second contact hole is covered with a second gate insulating film. A third semiconductor layer of the first conductivity type is formed in the second contact hole. The third semiconductor layer is in contact with the surface of the first gate electrode and extends from the surface of the first gate electrode to the substantially same level as a lower surface of the second gate electrode. A second channel semiconductor layer of the second conductivity type is formed in the second contact hole. The second channel semiconductor layer is in contact with a surface of the third semiconductor layer and extends from the surface of the third semiconductor layer to the substantially same level as an upper surface of the second gate electrode. A fourth semiconductor layer of the first conductivity type forming the other of the source/drain regions is formed in the second contact hole. The fourth semiconductor layer is disposed on the second channel semiconductor layer and is in contact with the surface of the second channel semiconductor layer. A second conductive layer of the first conductivity type is disposed on the third interlayer insulating film and is connected to the fourth semiconductor layer.
A tenth aspect of the invention relates to a semiconductor device including a gain cell. The semiconductor device of this aspect includes a substrate, and a first gate electrode of a second conductivity type disposed on the substrate. Source/drain regions of a first conductivity type are disposed at a main surface of the substrate and are located at opposite sides of the first gate electrode. A first interlayer insulating film covering the first gate electrode is disposed on the substrate. A second gate electrode is formed on the first interlayer insulating film. A second interlayer insulating film covering the second gate electrode is formed on the first interlayer insulating film. A contact hole, which penetrates the second gate electrode and the first interlayer insulating film, is provided for exposing a portion of a surface of the first gate electrode. A side wall of the contact hole is covered with a gate insulating film. A first semiconductor layer of a second conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first gate electrode and extends from the surface of the first gate electrode to the substantially same level as a lower surface of the second gate electrode. A channel semiconductor layer of the first conductivity type is formed in the contact hole. The first channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the second gate electrode. A third semiconductor layer of the second conductivity type forming the other of the source/drain regions is formed in the contact hole. The third semiconductor layer is disposed on the channel semiconductor layer and is in contact with the surface of the channel semiconductor layer. A conductive layer of the second conductivity type is formed on the second interlayer insulating film and is in contact with the third semiconductor layer.
An eleventh aspect of the invention relates to a semiconductor device including a matrix of a liquid crystal display. The semiconductor device of this aspect includes a first conductive layer of a first conductivity type which is disposed on a substrate and forms one of source/drain regions. A first interlayer insulating film is disposed on the substrate. A gate electrode having an upper surface and a lower surface is disposed on the first interlayer insulating film. A second interlayer insulating film covering the gate electrode is formed on the first interlayer insulating film. A contact hole, which penetrates the first interlayer insulating film, the gate electrode and the second interlayer insulating film, is provided for exposing a portion of a surface of the first conductive layer. A side wall of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first conductive layer and extends from the surface of the first conductive layer to the substantially same level as the lower surface of the gate electrode. A channel semiconductor layer is formed in the contact hole. The channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the gate electrode. A second semiconductor layer of the first conductivity type forming the other of the source/drain regions is formed in the contact hole. The second semiconductor layer is disposed on the channel semiconductor layer and is in contact with a surface of the channel semiconductor layer. A pixel electrode is connected to the second semiconductor layer.
A twelfth aspect of the invention relates to a method of manufacturing a semiconductor device in which a gate transistor is operable to store information in a capacitor formed of a storage node, which is arranged at a crossing between a bit line and a word line, a capacitor insulating film and a cell plate electrode. The method includes the step of preparing a substrate on which a dielectric member and a semiconductor layer are formed successively. A first conductive layer containing impurity of a first conductivity type is formed at a surface of the semiconductor layer. The first conductive layer forms one of source/drain regions and also forms the bit line. A first interlayer insulating film is formed on the substrate. A gate electrode, which forms the word line and has upper and lower surfaces, is formed on the first interlayer insulating film. A second interlayer insulating film is formed on the substrate to cover the gate electrode. A contact hole is formed. The contact hole penetrates the first interlayer insulating film, the gate electrode and the second interlayer insulating film, and reaches a surface of the first conductive layer. A side wall of the contact hole is covered with a gate insulating film. A second semiconductor layer is formed on the substrate. The second semiconductor layer is in contact with the surface of the first conductive layer, and fills the contact hole. Impurity of the first conductivity type is implanted into a surface of the second semiconductor layer. The impurity implanted into the surface of the second semiconductor layer is diffused into the second semiconductor layer, and the impurity contained in the first conductive layer is diffused from the first conductive layer into the second semiconductor layer, whereby a region, which forms the other of the source/drain regions and also forms the storage node, and a channel region, which is located between the other of the source/drain regions and the one of the source/drain regions, are formed at the second semiconductor layer. A capacitor insulating film is formed on the other of the source/drain regions. A cell plate is formed on the storage node with the capacitor insulating film therebetween.
According to the semiconductor device of the first aspect of the invention, since the semiconductor layer formed on the dielectric layer is used as the bit line, the capacitance of the bit line is reduced and a dynamic random access memory can operate at a high speed.
According to the semiconductor device of the second aspect of the invention, since the dummy V"PHgr"T is used, contact of the aluminum interconnection can be made easily.
According to the semiconductor device of the third aspect of the invention, since the bit line is commonly used by the upper and lower V"PHgr"T-DRAMs, the bit line can be formed only by one step, so that the number of manufacturing steps and thus a manufacturing cost can be reduce.
According to the semiconductor device of the fourth aspect of the invention, since the polysilicon, which fills the concave portion of the silicon thin film and is in contact with the channel portion, is used as the lead electrode, the potential of the channel portion can be fixed.
According to the semiconductor device of the fifth aspect of the invention, since there is provided the conductive member covering the side wall of the contact hole, it is possible to form a V"PHgr"T having a body of which a diameter is smaller than a minimum hole diameter attainable with a lithography technique. As a result, the body can be depleted completely.
According to the semiconductor device of the sixth aspect of the invention including the OR circuit, since the contact hole of the V"PHgr"T spreads over two gates, the circuit can be formed within a very small area.
According to the semiconductor device of the seventh aspect of the invention including the AND circuit, since the V"PHgr"T is used as a component of the AND circuit, the area occupied by the device can be small.
According to the semiconductor device of the eighth aspect of the invention including the inverter circuit, since the V"PHgr"T is used, the occupied area can be small.
According to the semiconductor device of the ninth aspect of the invention including the flip-flop circuit, since the V"PHgr"T is used, the occupied area can be small.
According to the semiconductor device of the tenth aspect of the invention including the gain cell, since the V"PHgr"T is used, the occupied area can be small.
According to the semiconductor device of the eleventh aspect of the invention including the matrix of the liquid crystal, since the V"PHgr"T is used, the occupied area can be small.
According to the method of manufacturing the semiconductor device of the twelfth aspect of the invention, since the semiconductor layer formed on the dielectric member is used as the bit line, the capacitance of the bit line can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.